- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com>
- Facebook Group: https://www.facebook.com/groups/system.software2026/
- Policy
- Course grading
- Quiz (30%), Homework (30%), Final/Term Project (40%)
- NOTICE: You MUST participate in at least one in-person oral discussion about quizzes or homework by December 29, 2026. After each discussion, you must follow up by email and obtain the instructor’s acknowledgment. Otherwise, you will receive no credit for any quizzes.
- Guidelines for Student Use of AI Tools
- Schedule is tentative and subject to change!
Computer Architecture (Fall 2026)
- Week 1 (Sep 8): Introduction
- Week 2 (Sep 15): Quiz
- Week 3 (Sep 22): RISC-V
- Week 4 (Sep 29): Quiz + RISC-V
- Week 5 (Oct 6): RV32I + Code Review
- Announcement
- In today’s class, we will discuss the progress of Homework 1 with the students. Whether you are voluntarily or non-voluntarily participating in the Q&A, you should follow the assignment guidelines, prepare your HackMD notes, and set them to public. When the instructor talks with you, you should paste the link to your HackMD notes for Homework 1 here. → 2025-10-07
- Quiz 3 is scheduled for Oct 21. Be sure to carefully review past quizzes, understand their level of difficulty, and practice thoroughly.
- Review: RISC-V Architecture Instruction Encoding
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Week 6 (Oct 13): Toolchain + Digital Systems
- Announcement
- Quiz 3 is scheduled for Oct 21 and will cover RISC-V assembly programming, software optimizations, instruction encoding, sequential logic, and combinational logic.
- The follow-ups for Quizzes 1 and 2, including lecture discussions and further improvements, have been updated in the syllabus. Please review them carefully.
- Homework 2 will be assigned next week, focusing on bare-metal programming, an essential skill for embedded system engineers. Search bare-metal via Google Career.
- Compiling, Assembling, Linking, and Loading / video-1 + video-2
- Freestanding RISC-V Programs
- Lab2: RISC-V for RV32I bare-metal programming
- Revisit Quiz 1
- Binary marble adding machine / video
- Yes, you can implement a few logic-like elements without electricity.
- Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
- Synchronous Digital Systems (SDS) / video
- Combinational Logic / video
- sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
- SDS State / video
- Combinational Logic Blocks / video
- Week 7 (Oct 20): Quiz
- Announcement:
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- Week 8 (Oct 27): Review + Datapath and Control
- Announcement:
- The textual description of Problem D in Quiz3 is correct, but the accompanying image is incorrect. As compensation, all participants of Quiz 3 will receive a 15-point increase.
- If you voluntarily participate in the class discussions for Quiz3, please email the instructor afterward, including your responses to the instructor’s questions and any follow-up contributions. You will receive an additional 10 points for Quiz 3.
- “What I cannot create, I do not understand.” - On Richard Feynman’s blackboard at the time of his death in 1988 / Build Your Own X
- video: Circuits recap
- RISC-V Datapath I / video
- RISC-V Datapath II / video
- Week 9 (Nov 3): Datapath and Control + Pipeline
- Announcement:
- Submit Homework 2 through Google Form.
- Homework 3 will be finalized on Nov 6
- Quiz 4 is scheduled for Nov 18
- Easy RISC-V
- an interactive tutorial created by dramforever that introduces the fundamentals of RISC-V assembly programming through hands-on experimentation. Inspired by Easy 6502, it uses a browser-based simulator to let learners observe every step of program execution — from instruction decoding to register and memory state changes — without requiring any software installation or toolchain setup.
- The tutorial focuses on the minimalist yet complete RV32I + Zicsr instruction set, guiding readers from their first simple instruction sequence (addi, ebreak) to more complex topics such as arithmetic and logic operations, branches, jumps, memory access, stack management, function calls, control and status registers (CSRs), privilege levels, exceptions, and even the construction of a bare-bones operating system.
- video: Are Computers Still Getting Faster?
- RISC-V Processor Design Control / video
- Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs.
- MIT 6.191 L15: Introduction to Pipelining, L16: Processor Pipelining
- Lab3: Construct a single-cycle CPU with Chisel
- Week 10 (Nov 10): Pipelined Processors
- Week 11 (Nov 17): Quiz + Homework Review
- Announcement
- In today’s class, we will discuss the progress of Homework 2 and Homework 3 with the students. Whether you are voluntarily or non-voluntarily participating in the Q&A, you should follow the assignment guidelines, prepare your HackMD notes, and set them to public. When the instructor talks with you, you should paste the link to your HackMD notes for Homework 2 here. → 2025-11-18
- Quiz4: RISC-V programming + datapath + control + pipelined processor / solution
- Homework1, Homework2
- Week 12 (Nov 24): Cache
- Announcement
- In today’s class, we will discuss the progress of Homework 2 and Homework 3 with the students. Whether you are voluntarily or non-voluntarily participating in the Q&A, you should follow the assignment guidelines, prepare your HackMD notes, and set them to public. When the instructor talks with you, you should paste the link to your HackMD notes for Homework 2 here. → 2025-11-18
- This semester, we will conduct 7 quizzes. Out of these, the best 4 will be selected for grading purposes.
- The instructor will submit the grades on the school’s designated deadline (Jan 23, 2026) for grade registration. This means that students will have ample time to dedicate to the final project assigned in this course.
- Term projects: Contact the instructor as early as possible. You must provide the materials and demonstrate to the instructor before Jan 20, 2026. Deliverables
- A development log and accompanying report
- Complete source code sufficient for full reproduction
- An illustrated video of at least 15 minutes.
- Quiz 5 is scheduled for Dec 9
- Cache (1) / video
- Cache (2) / video
- Cache (3) / video
- Cache (4) / video
- Recall: The golden age of ever-changing computer architecture
- Week13 (Dec 1): Virtual Memory + Operating System + Vector Extension
- Announcement
- In today’s class, we will discuss the progress of Homework 3 and Term project with the students. Whether you are voluntarily or non-voluntarily participating in the Q&A, you should follow the assignment guidelines, prepare your HackMD notes, and set them to public. When the instructor talks with you, you should update HackMD note here. → 2025-12-02
- Quiz 5 next week
- Virtual Memory
- The Future of Mission Critical Edge Compute Is RISC-V
- Lockstep systems are fault-tolerant computers that simultaneously perform identical operations in parallel. Borrowed from military marching terminology, these systems use redundancy to detect and correct errors. With two systems (dual modular redundancy), errors can be identified, and with three systems (triple modular redundancy), errors can be automatically corrected through majority voting.
- Customizing Linux Systems in Aerospace
- UCB: Operating Systems
- RISC-V Vector extension (RVV)
- Week14 (Dec 8): Quiz
- Announcement
- In today’s class, we will discuss the progress of Term project with the students. Whether you are voluntarily or non-voluntarily participating in the Q&A, you should follow the assignment guidelines, prepare your HackMD notes, and set them to public. When the instructor talks with you, you should update HackMD note here. → 2025-12-02
- Quiz5: pipelined processor + cache + virtual memory / solution
- Week15 (Dec 15): Operating System, Multithreading
- Announcement:
- Quiz6 is scheduled for Dec 23
- Term Projects: You must provide the materials and demonstrate to the lecturer before Jan 19, 2027
- The instructor sent an email on December 15 with the subject line “Re: CompArch: Term Project Assigned — Read Carefully and Start Logging Early”, outlining important guidelines and requirements for the term project. Students are required to read the email carefully and respond thoughtfully in accordance with the instructions provided.
- RISC-V Oral History Panel
- Ecosystem: Software is King
- Compiler First: The founders emphasized that an architecture is useless without a working C compiler. Early efforts focused heavily on porting GCC, LLVM, and Linux to ensure the hardware was actually usable.
- Community Power: By embracing open source, they allowed global developers to fix bugs and optimize performance, moving much faster than a single proprietary team could.
- Debunking CISC vs RISC code density
- Synchronization
- Please check your operating system textbook for such topic.
- Multithreading Issues + Cache Coherency
- video: The Future of Operating Systems on RISC-V / transcript
- Multithreaded Application Synchronization Part I / Part II
- Week16 (Dec 22): Quiz + Memory Model, I/O
- Week17 (Dec 29): Modern Processors
- Week 18 (Jan 5): Review