RISC-V RV32 Emulator
Fast interpreter with tiered JIT compilation | Zba/Zbb/Zbc/Zbs bit manipulation
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Display Output
Console Output
Features
Fast Interpreter
Tail-call-optimization based instruction dispatch with fusion for optimal performance on supported platforms.
Tiered JIT
Two-tier JIT compilation using LLVM 18 for hot code paths with block chaining optimization.
System Emulation
Boot full Linux kernel with device emulation including VirtIO, UART, and RTC support.
SDL Graphics
Graphics and audio support via SDL2 for running graphical RISC-V applications.